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Silicon Labs /Series0 /EFM32LG /EFM32LG280F128 /GPIO /ROUTE

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Interpret as ROUTE

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https://regviz.com/r/Silicon Labs/Series0/EFM32LG/EFM32LG280F128/GPIO/ROUTE#0x0

31282724232019161512118743000000000000000000000000000000000000000000 (SWCLKPEN)SWCLKPEN0 (SWDIOPEN)SWDIOPEN0 (SWOPEN)SWOPEN0 (LOC0)SWLOCATION0 (TCLKPEN)TCLKPEN0 (TD0PEN)TD0PEN0 (TD1PEN)TD1PEN0 (TD2PEN)TD2PEN0 (TD3PEN)TD3PEN0 (LOC0)ETMLOCATION

ETMLOCATION=LOC0, SWLOCATION=LOC0

Description

I/O Routing Register

Fields

SWCLKPEN

Serial Wire Clock Pin Enable
SWDIOPEN

Serial Wire Data Pin Enable
SWOPEN

Serial Wire Viewer Output Pin Enable
SWLOCATION

I/O Location

0 (LOC0): Location 0

1 (LOC1): Location 1

2 (LOC2): Location 2

3 (LOC3): Location 3
TCLKPEN

ETM Trace Clock Pin Enable
TD0PEN

ETM Trace Data Pin Enable
TD1PEN

ETM Trace Data Pin Enable
TD2PEN

ETM Trace Data Pin Enable
TD3PEN

ETM Trace Data Pin Enable
ETMLOCATION

I/O Location

0 (LOC0): Location 0

1 (LOC1): Location 1

2 (LOC2): Location 2

3 (LOC3): Location 3

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data